1. Field of the Invention
The present invention relates to a process for fabricating a metal interconnect, and more particularly, to a damascene process capable of avoiding via resist poisoning.
2. Description of the Prior Art
At present, metal interconnects of the sub-90 nm integrated circuit manufacturing process are formed by the damascene process and with a 193 nm resist. The damascene process etches a dielectric layer to form a pattern of a metal conductor wire, and then fills the pattern with metal. However, the conventional process needs to dry etch a metal layer and then fill the dielectric layer. Therefore, the damascene process is very important in metal interconnect manufacturing that is unsuitable to dry etch a metal layer, such as Cu. The damascene process could be sub-classified into a single damascene process and a dual damascene process.
Please refer to FIG. 1 to FIG. 3, which show the process schematics according to the single damascene of the prior the art. As shown in FIG. 1 to FIG. 3, the single damascene of the prior art could be classified into the following three main stages after finishing the conductor plug of the pre-layer (not shown). In the first-stage, as shown in FIG. 1, a base layer 10, such as SiN, is deposited. Next, a low-k dielectric layer 12 is deposited over the base layer 10 followed by a SiC layer 14 being deposited over the low-k dielectric layer 12. In the second-stage, as shown in FIG. 2, a bottom anti-reflection coating (BARC) layer 16 is formed over the SiC layer 14, a resist layer 18 having a opening 19 to exposure a portion of the BARC layer 16 is formed over the BARC layer 16. In the third-stage, as shown in FIG. 3, a single damascene structure 12 is formed in the low-k dielectric layer 12 by etching through the BARC layer 16 and the SiC layer 14 and etching the low-k dielectric layer 12. Then, a metal layer is deposited (not shown). A CMP process removes the metal residues over the low-k dielectric layer 12.
Please refer to FIG. 4 to FIG. 10, which show the process schematics according to the dual damascene of the prior art. As shown in FIG. 4 to FIG. 10, the dual damascene of the prior art could be classified into the following seven main stages after finishing the conductor wire of the pre-layer (not shown). In the first-stage, as shown in FIG. 4, a base layer 20, such as SiN, is deposited. A low-k dielectric layer 22 is deposited over the base layer 20. A SiC layer 24 is deposited over the low-k dielectric layer 22. A metal layer 26 is deposited over the SiC layer 24 to be a hard mask. A first BARC layer 28 is deposited over the metal layer 26. A dielectric layer (not shown) could be set between the metal layer 26 and the first BARC layer 28. A first resist layer 32 is formed having a trench opening 30, called a trench photo. In the second-stage, as shown in FIG. 5, a trench structure 34 is formed by etching through first BARC layer 28, the metal layer 26, and a portion of the SiC layer 24 through the trench opening 30. In the third-stage, as shown in FIG. 6, the first resist layer 32 and the first BARC layer 28 are removed.
In the fourth-stage, as shown in FIG. 7, a second BARC layer 36 is deposited over the SiC layer 24 and the metal layer 26, the second BARC layer 36 filling the trench structure 34. Next, a second resist layer 40 is formed having a via opening 38, called as via photo. In the fifth-stage, as shown in FIG. 8, a via structure 42 is formed by etching through the second BARC layer 36, the SiC layer 24, and a portion of the low-k dielectric layer 22 through the via opening 38.
In the sixth-stage, as shown in FIG. 9, the second resist layer 40 and the second BARC layer 36 are removed. In the seventh-stage, as shown in FIG. 10, a dual damascene structure having the trench and the via structure is formed in the low-k dielectric layer 22 by using the metal layer 26 and the SiC layer 24 as masks. Then, a metal layer (not shown) is deposited over the low-k dielectric layer 22. A CMP process removes the metal residues on the low-k dielectric layer 22.
However, a serious problem in the damascene process of the prior art is a via resist poisoning phenomenon. The above low-k dielectric layers 12, 22 of the damascene process of the prior art contain unpolymerized precursors. The unpolymerized precursors diffuse out from the low-k dielectric layers 12, 22, and the thickness of the SiC layers 14, 24 is insufficient to prevent unpolymerized precursors diffused out from the low-k dielectric layers 12, 22 from contacting an overlying resist. The unpolymerized precursors react with the subsequent resist layers 18, 22 to form a resist scum defect or via missing defect.